In order to perform design exploration even faster, these multi-PAR tasks can now be distributed to run in parallel on computers with a multi-core CPU. To improve timing closure productivity, users can now set up the multi-PAR placement and routing tool to stop after either trying a maximum number of seeds (or starting points) or when the last seed run has resulted in timing closure - whichever comes first.
This information can be exported to a text or a CSV file to enable analysis in other tools. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. Device resources can therefore be reported out as both logical (registers) and physical (slices) elements. Lattice Diamond 1.4 software now provides a report of device resources used by level of design hierarchy following either the synthesis or the map step (a process that maps the synthesis output to the device resources). In particular, a new System Planner tool aids optimizing resource usage, and multiple improvements have been made to the generation of DSP blocks.ĭesign Exploration Improves Time to Market Lattice Diamond 1.4 provides a complete set of powerful tools specifically targeted to the LatticeECP4 family's unique logic fabric and its built-in hardened IP blocks to enable lower cost and lower power applications. Select customers will be able to use Lattice Diamond 1.4 software to design with these new devices. With Lattice Diamond 1.4 software, users can now design and analyze using the most current data when targeting MachXO2 devices.Įarly Access to the New LatticeECP4 FPGA FamilyĪnnounced on November 28th, the LatticeECP4 FPGA family redefines the low cost, low power mid-range FPGA market for cost and power-sensitive wireless, wireline, video and computing markets. The final simultaneous switching output (SSO) data is available for all packages (except the wafer-level chip scale package of the LCMXO2-2000U, which will be made available later). Lattice Diamond 1.4 software now includes final data for timing, power, package and bitstream based on the actual silicon characterization of all the MachXO2 devices. The Lattice Diamond design environment enables users to easily explore design alternatives as they target cost-sensitive, low power, high volume applications - the type of applications ideally suited for the MachXO2 PLD family.
Lattice Diamond 1.4 software offers the right combination of FPGA tools with enhanced usability to rapidly close the timing of design critical paths, which is especially important for low power and cost-sensitive FPGA applications," said Mike Kendrick, Lattice's Director of Software Marketing.įinal Data Support for the MachXO2 PLD Family "Achieving timing closure in the shortest amount of time can be a significant challenge as users try to pack more and more functionality into a single FPGA. Also, using the Lattice Diamond 1.4 software, select customers can begin designing with the newly announced low cost, low power mid-range LatticeECP4™ FPGA family. In addition, Lattice Diamond 1.4 software enhances support for the MachXO2™ PLD family by providing final production timing, power models and bitstreams for the entire family, including the latest wafer-level chip scale packaged version of the LCMXO2-2000U and LCMXO2-1200U devices that are ideal for very high volume, cost- and power-sensitive applications.
Users of Lattice Diamond 1.4 software will benefit from several usability enhancements that make FPGA design exploration easier and reduce time to market. HILLSBORO, OR - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced release 1.4 of its Lattice Diamond(R) design software, the design environment for Lattice FPGA products.
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